Processing systems, such as microprocessors and microcontrollers, often utilize one or more caches to store information expected to be used by the processing system, thereby reducing the frequency of memory access operations and the resulting processing delays. Some processing systems employ an instruction cache to store instructions and a separate cache to hold data. This organization is commonly referred to as a “Harvard” cache arrangement. In contrast to the Harvard cache arrangement, “unified” caches hold both instruction information and data information in a common cache for use by the processing system. In certain embodiments, unified caches have a power and cost advantage. These caches frequently are implemented as set-associative caches having multiple ways in an effort to balance the benefits and disadvantages of direct-mapped caches and fully-associative caches. During a cache access, the way associated with the address is identified and the corresponding cache line of the identified way is accessed to obtain the stored data or to write data to the cache line.
While the implementation of set-associative caches often reduces processing delays, such caches often require substantial power and can significantly increase the overall power consumption of a processing device. The power consumed by a cache often has a number of drawbacks, such as increased cost of operation, reduction in effective battery time for portable devices, excessive heat generation, and the like. The power consumption of a set-associative unified cache is particularly problematic as only one way is utilized at any given time while the remaining ways continue to draw power even though they are not in use. Accordingly, a technique for reducing the power consumption of a unified cache would be advantageous.